U.S. Pat. No. 4,866,508 describes a plural-chip integrated circuit in which a number of monolithic integrated-circuit chips are flush-mounted in wells located on the surface of a common substrate and covered over with an insulating polyimide layer. These chips are connected to each other and to on-substrate metallization by High Density Interconnection (HDI) technology. The HDI connections are made through vias in the polyimide layer to bond pads as small as 25 microns across, which can be placed anywhere on the surfaces of the monolithic i-c chips or on the substrate; and connections can be made routing right over active portions of the integrated circuits by virtue of the intervening insulating polyimide layer. Up to four layers of metal interconnection separated by insulating polyimide layers may be used. A limited number of conventional-size bond pads allowing for plural-chip i-c pin-out are provided on the substrate.
Also described is the testing circuitry included within each monolithic i-c chip. Each chip includes a serial-in/parallel-out (SIPO) register for receiving a succession of test vectors supplied thereto in bit-serial form and for cyclically applying that succession of test vectors in bit-parallel form, either to the input ports of the chip or to each output port of each preceding chip as selected by test mode signals. Each chip includes a parallel-in/serial-out (PISO) register for receiving test results in parallel-bit form, either from the output ports of the chip or from each input port of each succeeding chip as selected by test mode signals, and converting the test results to bit-serial output form. The SIPO registers on the chips are also provided with serial-out capabilities, permitting their cascade interconnection as an extended shift register, through which test vectors supplied in serial form may be successively written to each of the SIPO registers. Similarly, the PISO registers on the chips are also provided with serial-in capabilities, permitting their cascade interconnection as another extended shift register, through which test results may be successively read in serial form from each of the PISO registers.
A problem encountered in testing using the approach described in U.S. Pat. No. 4,866,508 is that access times become excessively long as the number of chips in a plural-chip integrated circuit increases, especially if the number of ports being tested per chip increases, causing increases in the lengths of the extended shift registers used for writing in test vectors to a test input port on one of the chips in the digital electronics system and for reading out test results from a test output port on that chip or another. Testing is usually carried out by isolating chunks of electronic circuitry located in respective portions of one or more monolithic integrated circuits and then subjecting the chunks to testing one at a time. (In interconnection testing, a pair of chunks at opposite ends of an interconnection are selected for testing at any one time). The successive input test patterns each have to be clocked completely through the cascaded SIPO registers for test input data before the next test pattern is entered. So substantial time is taken up during testing just to properly locate input test data in the cascade connection of SIPO registers for test input data. There is the further problem of the shifting of test output results from an extended PISO register adding to the time taken up by testing.
The problem of the extended times for testing a chunk at a time can be avoided by testing several chunks, in parallel, at the same time. However, this undesirably complicates the design of programs for automatically generating test sequences working from a software description of digital system internodal connections. To simplify the design of such programs, it is highly desirable to be able to specify on a selective-access basis the ports in a digital electronics system to which test input data are to be applied in bit-serial form and from which test output results are to be taken in bit-serial form.
Such selective access can be provided by some form of multiplexing to ports for applying test input data and from ports for sensing test output responses, it can be postulated. The problem is to develop multiplexing circuitry for test input data and test output results that can be extended over as many portions of digital electronic systems as one may seek to test. It is desirable to use local switching circuitry for multiplexing the SIPO test input data registers. It is also desirable to use local switching circuitry for multiplexing the test output results in real time, so as to be able to avoid the delays occasioned by the use of PISO test output data registers.
A method of providing for multiplexing used in the data communication arts is token passing, wherein local switching circuits pass among them a token (e.g., a logic ONE electric signal) possession of which grants access to a shared communications channel. Schemes are known in which transceiver stations pass only one token among themselves to determine which single transceiver shall be able to transmit data over the shared communications channel, with all transceivers not possessing the token being conditioned only to receive data. Plural token passing schemes are also known. In one such scheme transceivers pass two tokens along separate paths, the first token determining which single transceiver can transmit over the channel and the second token determining which single transceiver can receive the transmission. Plural token passing schemes are known where the path for passing the second token can contain further tokens enabling selected transceivers to receive. Relaying schemes are known where the transceivers use one communications channel and pass both the first token enabling reception and the second token enabling transmission along the same path, one after the other. None of these prior-art token passing schemes in which a shared communications channel is used simultaneously by a plurality of transceivers is appropriate for use in testing selected portions of an electronics system.
Token passing is utilized in the invention for controlling the multiplexing of bit serial input data to portions of an electronics system under test and for controlling the multiplexing of bit-serial test results from portions of the electronics system under test, so the switching circuitry for carrying out the multiplexing of each portion of the electronics system can be local. During testing there are two channels being assigned using respective tokens. One channel is used for controlling the application of test signals and sequencing of testing and the other channel is used for extracting test results. A single portion of the electronics system under test uses both channels and does not communicate to other portions of the electronics system.
A plural-dimension addressing scheme devised by the inventors uses token passing to select the monolithic integrated circuit involved in testing (or pair of circuits interconnections between chunks involved in testing) and uses additional token passing to select the specific chunk (or pair of chunks) involved in testing.
Token passing involves a positional code and requires considerably more bits than a binary number code to indicate a selection. The shift register for implementing token passing to determine which of a set of successive ports is to be tested has reduced latency as compared to the extended test input data SIPO register, however, to and the extended test output result PISO register as well. This is because the token is normally only one bit or a few bits long, rather than several bits long as is the case with test input data and test output results. The use of binary number codes to control local switching circuitry forming the multiplexers is possible, as already noted, but the number of control lines required to convey the binary number bits in parallel is larger than one would like. Bit-serial transmission schemes for the binary number codes tend to involve the latency problem in another form, especially if the codes are made self-parsing to avoid the need for two control lines.